Circuits enabling both high performance and low power
To make entire IoT system energy efficient, the data sensed by a sensing device must be filtered so that only data with low entropy can be selectively transmitted into data center. Thus, sampling data would have to be temporally stored in low power non-volatile memory. Fast and power efficient array access minimize energy per bit. We need to find the best way of controlling the neo-volatile memory array. Another area of concern on lower power emerging non-volatile memory is normally-off computing. It aims at reducing power in computing relying on non-volatile switching devices using spin or resistive memory technology. Microprocessor is powered off normally to make stand-by power zero. Right before microprocessor starts running, it is powered up and the data of the internal memories such as registers are loaded down from the non-volatile memory which stores the previous data before power-off and is located closely to the registers. When the stand-by power is the major part of the average power, and when the power for reading (writing) the data from (into) the non-volatile memory is sufficiently low, the system power can be reduced significantly by repeating power- on and off. Consequently, it is a key to design low power sensing and control circuits for the emerging non-volatile memory. We would like to contribute to circuits and systems design in this research area as well.
We have started with research on a closed-form expression for pre-emphasis pulses with minimal RC delay time, which was presented at IEICE general conference in March of 2018.
Animation 1: Much faster pre-charging with pre-emphasis pulses compared with step pulses
Animation 2: Optimum pre-emphasis pulse compared to non-optimum ones
Animation 3: Different waves with different wave numbers vary at each own time constant.
