~ What I have learned through the research on charge pump circuit design ~ Toru Tanzawa
Education
I joined a newly launched small mathematics club in the last year of my high school in 1986 where Yamagiwa sensei, a teacher of mathematics, gave us one interesting problem in mathematical physics at a time and discussed how to solve it at the next time every two weeks. Club members had two weeks to think about the problem. I remember that I often so concentrated on the problem that I couldn’t pay attention to the other subjects. That had both pros and cons, but I believed the pros overweighed the cons for me. Thanks to the teacher, mathematical physics became my enthusiasm. Thus, it was natural for me to select physics as the major in the university.
When I graduated the university in 1990, I still wanted to continue to study theoretical physics in a graduate school. A main teacher of mine, Professor Takagi, who has taught me logical thinking in addition to physics, suggested a theory of quantum mechanics as the theme for my master’s degree. It was very excited when two papers have been published from Progress of theoretical physics based on my master’s thesis even though the first authors were not myself.
In the second year of master’s degree, I have visited several high-tech companies such as semiconductor and telecommunication companies for a job interview. At that time, graduates were able to select a company rather than companies selected a graduate in a labor market. The words that grabbed me most were Dr. Masuoka, a director of Toshiba at that time and a professor emeritus of Tohoku university now; “you should join us if you want to do something to be the best in the world”. It brought me to ULSI R&D center of Toshiba in 1992 even though I didn’t know what transistors are and how they work at that moment. Luckily, Dr. Masuoka had run one year course for the new entrants so that they could learn broad aspects about semiconductor physics while research cutting edge topics in their teams. I can never thank him enough for providing very interesting first year of my carrier.
When I joined R&D center of Toshiba, I set a target to myself to become Ph. D by 30 years old. There is a system in Japan that any employee can have a chance to ask a university to qualify them as Ph. D. I did so to Prof. Sakurai of the University of Tokyo. I met him at VLSI circuit symposium in 1996 where he served as the program chair and recommended my conference paper to Journal of Solid-State Circuits. Another luck was that he accepted my request for being the chief examiner of my Ph. D thesis of “Low voltage circuit design for high-performance Flash memories”. Even though I had had several journal papers till 2000, it was not easy work for me to make them into a single thesis. I can recall the day when Prof. Sakurai discussed the thesis from the first chapter to the last chapter for continuous six hours with great passion and no break. I exhausted my energy and so felt a little sick after the discussion. At last after publishing two additional journal papers, my thesis reached the point where the examiner committee recognized me as Ph. D with strong support from Prof. Sakurai in 2002. I don’t know how to express my thanks to him.
Education is not always made by a teacher or professor. Attending international and domestic conferences have also educated me. Even though paper presentations are not directly associated with semiconductor memory technology, they often give me a clue to come up with something innovated in circuit design for semiconductor memory. Both Toshiba and Micron have allowed me to submit conference papers and to attend conferences as far as the paper doesn’t include any confidential matter or IP. I appreciate both companies on providing me great chances.
Another opportunity of learning is when a product issue appeared. The root cause is usually a simple design bug, but sometimes a fundamental technical issue. The issue requires something innovated in order for us not to occur issues originated with the same root cause again. Problems as well as necessities call for innovation.
Research with Toshiba
When I joined Toshiba ULSI R&D center, I was assigned to NAND team where the members were not more than ten at that time. They just developed very first NAND test vehicle with 4M-bits density operating at 5V. A supervisor of mine, Tomoharu-san, provided me an interesting topic about charge pumps which generate program/erase voltages on chip. It is one of the most critical circuit blocks to operate NAND with a single power supply and to reduce the supply voltage for low power.
A charge pump circuit is composed of multiple stages, each of which has a capacitor and a switch. When one needs to generate a programming voltage of 25V from a supply voltage of 3V, the charge pump has to have more than their ratio, e.g., 10 stages or more. Only steady state model was known in literature at that moment. I was not able to use it for dynamic analysis as it was. As a first trial for my understanding on how it works, I investigated dynamics of a single stage charge pump. The capacitor inputs the charges from the supple voltage source in a first half cycle of a clock and outputs them to the output terminal in a second half cycle. Thus, the capacitor and output voltages increase gradually. I noticed that the current and next states of the capacitor and output voltages could be related as a recurrence formula, and solved it analytically. When the number of stages were more than one, it seemed that the recurrence relations could be solved not analytically, but numerically. It enabled us to calculate the rise time when the design parameters such as the capacitance per stage, the number of capacitors, the capacitance of the load, the clock frequency, the supply voltage and the output voltage, are given.
How should the charge pump circuit be optimally designed? When the circuit area is given, the multiple of the number of stages and the capacitance of the stage capacitor needs to be a constant. When the number of stages increases much, the rise time would increase because the stage capacitor decreases accordingly. Conversely, the number of stages decreases much, the output voltage couldn’t reach the target voltage. As a result, there must be an optimum condition between those two extremes to have the shortest rise time. One can figure it out based on the simulation results repeatedly. However, you would have to do the same when the condition is changed. To answer the optimization question generally, you may want to find a dynamic model of the charge pump for the analytical optimization. Then, I tried to calculate the transient operation in two independent methods.
One way is to calculate an integration of the total input charges from the start to the end when the output voltage reaches the target by multiplying the output current by a factor of the number of stages plus one. The other is to calculate the input total charges directly as follows; the driver for the last stage capacitor is supposed to input the charges as much as an increase in the charges stored in the load capacitor during the rise time. Similarly, the driver for the capacitor next to the last stage is supposed to input the charges as much as an increase in the charges stored in the load capacitor and the last stage capacitor during the rise time. After doing the same step till the input, one can calculate the total input charges by adding all of them. Those with the first and second methods must be equal. As a result, I was able to find the analytical form to express the dynamics of the charge pump.
The equation indicates an equivalent circuit composed of an effective voltage source and resistor describing the steady state operation and an effective capacitor describing the transient behavior. The effective capacitor represents an effect of the internal capacitance of the charge pump with an amount of about one-third of the total capacitance. Because each of the voltage source, resistor and capacitor is given by circuit parameters, I was able to do the optimization analytically as I wanted before. When one designs the charge pump to have the number of stages to be 1.4 times larger than the minimum number of stages in case of the supply voltage and the target high voltage given, the rise time can be minimal. I felt I was happy at the moment when I reached that conclusion which has never been known in literature. I don’t doubt that the happiness was the result of combination of the best timing that I have researched the theme, the background that I have learned theoretical physics, and the NAND team which was rich in humor. Thus, the dynamic analysis of the charge pump circuits became the first IEEE paper of mine in 1997. It has been cited by over 300 papers probably because it describes a simple charge pump model to easily understand how it works and to show how an optimum number of stages is determined.
That was not a unique optimization question. It was also important questions to maximize the output current with a given circuit area and to minimize power. For example, what if the design minimizing the rise time consumes power much and what if the power is one of issues? You cannot forget such a trade-off. You need to make a balance between the two or more.
Dr. Masuoka showed three things that is expected for engineers in his laboratory; 1. Patent, 2. Paper, 3. Product. The order must be valid while NAND was under R&D phase. But these three P’s might have been rearranged after competition in NAND market place started in early 21st century; 1. Product, 2. Patent, 3. Paper. The first priority is now making competitive NAND products. We need to innovate something to make the products competitive, which results in patent. It may be not so attractive for most of engineers to write a paper, but it adds to our knowledge each other if it is published in journal and conference papers, which can make others encourage to think more. Thus, engineers can be happy with their work by spending a part of their work time for something enjoyable with those three P’s.
Research with Micron
I continued to think about the circuit analysis and optimization questions even after I joined Micron Japan, Ltd. (Micron Memory Japan, Inc. now) in 2004. As soon as I came up with publishing a book on integrated high-voltage circuits around 2010, I started gathering my knowledge in literature including my IEEE papers. But, the number of pages was about 100 at most. Any publisher wouldn’t be interested in such a short book. I realized some important works were left to be done after I compiled chapters and sections into a single article. Without doing that, I couldn’t have identified what I should do next. Since then, I have spent almost every weekend to study modeling of high-voltage circuits at home. First, I grappled with the question why IC industry had used a specific topology among various types. One of them was a so-called Cockcroft-Walton multiplier which Cockcroft and Wonton used to demonstrate fission of Li nucleus one century ago. There must be a reason, but it was not clear. I constructed a systematic way to compare circuit area and power efficiency between different topologies, which concluded that the specific topology had the least sensitivity on parasitic capacitance inherent to integrated high-voltage circuits. Then, I focused on how the circuits should be optimally designed in terms of circuit area or power efficiency. Lagrange’s method was effective to solve the problems. I also pursued to have opportunity of a tutorial presentation at IEEE conference because I thought that should end up with an increase in the number of figures which can make a future book more understandable. It was very fortune for me that an editor of a publisher asked me to publish a book based on the tutorial presentation at ISCAS (international symposium on circuits and systems) in 2010. I reorganized the chapters for the final version of the first edition, On-Chip High-Voltage Generator Design, and finally published it in 2013 with strong support from editors of the publisher.
Both companies that I was involved in were very open-minded. Each of them has allowed me to submit papers. That was another major factor in that I felt my happiness. Any submitted paper was not accepted at the initial review. Some papers were accepted at the final review after revising them. The others were failed for publication via the journal that I submitted. In those cases, I further revised them for submission to the other journals. In the longest case, I needed to repeat it four times. One of my favorite quotes is “There is no failure except in no longer trying” by Elbert Hubbard.
What I have learned from the research
If you have fortune that you can join a team who is aiming to be the best in the world in a field and that the research is allowed to proceed over a certain time period, you should have a moment to feel you are happy when you solve a question whose answer hasn’t been known. Even if you don’t have such fortune, you could pursue your question in your own time. Wouldn’t it be a happy moment when you reached a point where only you know its answer while anyone else doesn’t. Let’s think about the next question.
June 23, 2017