Design for high reliability
As memory devices and transistors are scaled, process and device variations increases inherently. Circuits and systems designs need to mitigate the variations. In the journal and conference papers (c10a, c10b, c04a, p97a), circuits for error correction, temperature compensation and negative-bias temperature instability (NBTI) for NAND Flash memory are proposed and developed. The error correction circuit reduces the area and peak power significantly so that it can be integrated into NAND die. The temperature compensation circuit for NAND Flash reduces the voltage margins between adjacent threshold levels which have been needed for a conventional circuit. As a result, bit error rate can be reduced when program is made at high temperature and read is made at low temperature or vice versa. The temperature compensation circuit for a voltage-controlled oscillator in 1-chip Bluetooth LSI reduces a frequency drift by intentionally varying the capacitance of variable capacitors. The NBTI mitigation circuit enables to scale high-voltage transistors, i.e., to reduce the decoder circuit area.
