研究成果

英論文誌

  1. Tadatoshi SEKINE, Yuichi TANJI, and Hideki ASAI, “Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-based Fast Simulation for Power/Ground Plane,” IEICE Transactions on on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 9, pp. 2450-2455, Sep. 2008.
  2. Tadatoshi SEKINE, and Hideki ASAI, “CMOS Circuit Simulation Using Latency Insertion Method,” IEICE Transactions on on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 10, pp. 2546-2553, Oct. 2009.
  3. Tadatoshi Sekine, and Hideki Asai, “Block-Latency Insertion Method (Block-LIM) for Fast Transient Simulation of Tightly Coupled Transmission Lines,” IEEE Transactions on Electromagnetic Compatibility, vol. 53, no. 1, pp. 193-201, Feb. 2011.
  4. Tadatoshi Sekine, Yohei Oikawa, and Hideki Asai, “Stabilized Mixed Finite-Element Time-Domain (FETD) Method for Fast Transient Analysis of Multiscale Electromagnetic Problems,” IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 10, pp. 4346-4356, Oct. 2018.

英論文誌(共著)

  1. Yuta Inoue, Tadatoshi Sekine, Takahiro Hasegawa, and Hideki Asai, “Fast Circuit Simulation Based on Parallel-Distributed LIM using Cloud Computing System,” Journal of Semiconductor Technology and Science, vol. 10, no. 1, pp. 49-54, Mar. 2010.
  2. Hiroki Kurobe, Tadatoshi Sekine, and Hideki Asai, “Alternating Direction Explicit-Latency Insertion Method (ADE-LIM) for the Fast Transient Simulation of Transmission Lines,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 2, no. 5, pp. 783-792, May 2012.
  3. Hiroki Kurobe, Tadatoshi Sekine, and Hideki Asai, “Locally Implicit LIM for the Simulation of PDN Modeled by Triangular Meshes,” IEEE Microwave and Wireless Components Letters, vol. 22, no. 6, pp. 291-293, Jun. 2012.
  4. Yuta Inoue, Tadatoshi Sekine, and Hideki Asai, “Parallel-Distributed Block-LIM for Transient Simulation of Tightly Coupled Transmission Lines,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 3, no. 4, pp. 670-677, Apr. 2013.
  5. Takahiro Takasaki, Tadatoshi Sekine, and Hideki Asai, “Fast Transient Analysis of Nonuniform Multiconductor Transmission Lines Using HIE-Block-LIM,” IEEE Microwave and Wireless Components Letters, vol. 23, no. 10, pp. 512-514, Oct. 2013.
  6. Hideaki Muraoka, Yuta Inoue, Tadatoshi Sekine, and Hideki Asai, “A Hybrid Implicit-Explicit and Conformal (HIE/C) FDTD Method for Efficient Electromagnetic Simulation of Nonorthogonally-Aligned Thin Structures,” IEEE Transactions on Electromagnetic Compatibility, vol. 57, no. 3, pp. 505-512, Jun. 2015.
  7. Shingo Okada, Tadatoshi Sekine, and Hideki Asai, “Multi-Rate Locally Implicit Block Leapfrog Scheme for Fast Transient Analysis of Multi-Layered Power/Ground Planes,” IEEE Microwave and Wireless Components Letters, vol. 26, no. 6, pp. 377-379, May 2016.

和論文誌

  1. 關根惟敏, “共形等価回路と回路指向型Leapfrog ADI法に基づく多層電源分配回路網の高速シミュレーション”, 電子情報通信学会論文誌B, vol. J102-B, no. 3, pp.248-257, 2019年3月

和論文誌(共著)

  1. 井上雄太, 關根惟敏, 浅井秀樹, “GPGPU-LIMを用いた電源分配回路網の高速過渡解析”, 電子情報通信学会論文誌C, vol. J93-C, no. 11, pp. 406-413, 2010年11月
  2. 石丸友紀, 關根惟敏, 浅井秀樹, “ADIブロックLIMによる多層電源分配網解析”, 電子情報通信学会論文誌A, vol. J94-A, no. 12, pp. 1043-1046, 2011年12月
  3. 高崎貴大, 關根惟敏, 浅井秀樹, “節点ブロック緩和法を用いた不均一な多導体伝送線路の高速過渡解析”, 電子情報通信学会論文誌C, vol. J96-C, no. 6, pp. 114-121, 2013年5月
  4. 岡田慎吾, 關根惟敏, 浅井秀樹, “局所陰的ブロック型Leapfrog法による多層電源分配網の高速過渡解析”, 電子情報通信学会論文誌C, vol. J98-C, no. 5, pp. 96-104, 2015年5月

総説・解説(共著)

  1. 浅井秀樹, 井上雄太, 關根惟敏, “高速三次元電磁界・回路シミュレーション技術の現状と将来展望 ―アルゴリズムと並列計算の観点から―”, 電子情報通信学会 基礎・境界ソサイエティ Fundamentals Review, vol. 7, no. 3, pp. 197-209, 2014年1月

講演

  1. 【招待講演】關根惟敏, “電源分配回路網の高速シミュレーションに向けた回路指向型モデル化・解析手法”, 電子情報通信学会 回路とシステム研究会, 信学技報, vol. 116, no. 467, CAS2016-128, p. 81, 2017年2月

講演(共著)

  1. 【記念講演】高崎貴大, 關根惟敏, 浅井秀樹, “HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines”, 電子情報通信学会VLSI設計技術研究会, 信学技報, vol. 113, no. 454, VLD2013-155, pp. 115-118, 2014年3月

受賞

  1. 關根惟敏, 電子情報通信学会東海支部 学生研究奨励賞, 電子情報通信学会東海支部, 2011年6月
  2. 關根惟敏, 静岡大学創造科学技術大学院長賞, 静岡大学創造科学技術大学院長, 2011年9月
  3. Tadatoshi Sekine, IEEE International Conference Presentation Student Award, IEEE Nagoya Section, Dec., 2011
  4. 關根惟敏, システムと信号処理サブソサエティ貢献賞, 電子情報通信学会システムと信号処理サブソサエティ, 2017年5月

受賞(共著)

  1. 石丸友紀, 關根惟敏, 浅井秀樹, 電子情報通信学会回路とシステム研究会 学生優秀賞, 電子情報通信学会回路とシステム研究会, 2010年3月
  2. 井上雄太, 關根惟敏, 浅井秀樹, 電子情報通信学会回路とシステム研究会 学生優秀賞, 電子情報通信学会回路とシステム研究会, 2010年3月
  3. Yuta Inoue, Tadatoshi Sekine, Takahiro Hasegawa, and Hideki Asai, ITC-CSCC 2009 Outstanding Paper Award, ITC-CSCC 2009, Jul., 2010
  4. 石丸友紀, 關根惟敏, 浅井秀樹, 第25回エレクトロニクス実装学会春季講演大会 研究奨励賞, エレクトロニクス実装学会, 2011年3月
  5. 黒部裕貴, 關根惟敏, 浅井秀樹, 電子情報通信学会回路とシステム研究会 学生優秀賞, 電子情報通信学会回路とシステム研究会, 2011年3月
  6. 井上雄太, 關根惟敏, 浅井秀樹, JPCA Show アカデミックプラザ 2012 アカデミックプラザ賞, JPCA Show 2012, 2012年6月
  7. 岡田慎吾, 關根惟敏, 浅井秀樹, 第158回システムLSI設計技術研究会 優秀発表学生賞, 情報処理学会システムLSI設計技術研究会, 2013年8月
  8. 岡田慎吾, 關根惟敏, 浅井秀樹, 平成25年度 システムLSI設計技術研究会 優秀論文賞, 情報処理学会システムLSI設計技術研究会, 2013年8月
  9. Takahiro Takasaki, Tadatoshi Sekine, and Hideki Asai, ASP-DAC 2014 Excellent Student Award, ASP-DAC 2014, Jan., 2014
  10. 及川陽平, 關根惟敏, 浅井秀樹, 電子情報通信学会回路とシステム研究会 学生優秀賞, 電子情報通信学会回路とシステム研究会, 2018年3月

国際会議

  1. Tadatoshi Sekine, Yuichi Tanji, and Hideki Asai, “Application and Estimation of Relaxation-Based Simulation Techniques to Interconnect and Plane Networks,” in Proc. NOLTA2007, Vancouver, Canada, pp. 517-520, Sep. 2007.
  2. Tadatoshi Sekine and Hideki Asai, “Application of Latency Insertion Method to CMOS Circuit Simulation,” in Proc. NOLTA2008, Budapest, Hungary, pp. 440-443, Sep. 2008.
  3. Tadatoshi Sekine and Hideki Asai, “CMOS Circuit Simulation Using Latency Insertion Method,” in Proc. IEEE EPEP 2008, San Jose, CA, pp. 55-58, Oct. 2008.
  4. Tadatoshi Sekine and Hideki Asai, “Hybrid Analysis of Large Interconnects and Nonlinear Circuit Using Hierarchical Technique,” in Proc. NCSP’09, Honolulu, HI, pp. 538-541, Mar. 2009.
  5. Tadatoshi Sekine and Hideki Asai, “Block Latency Insertion Method (Block-LIM) for Fast Transient Simulation of Tightly Coupled Transmission Lines,” in Proc. 2009 IEEE International Symposium on EMC, Austin, TX, pp. 253-257, Aug. 2009.
  6. Tadatoshi Sekine and Hideki Asai, “Generalized Leapfrog Scheme for Large-Scale Circuit Simulation,” in Proc. IEEE EPEPS 2009, Portland, OR, pp. 81-84, Oct. 2009.
  7. Tadatoshi Sekine and Hideki Asai, “Iterative Latency Insertion Method for Large Networks with Low Latency,” in Proc. IEEE EPEPS 2010, Austin, TX, pp. 161-164, Oct. 2010.
  8. Tadatoshi Sekine and Hideki Asai, “Mixed Finite Element Time Domain Method Based on Iterative Leapfrog Scheme for Fast Simulations of Electromagnetic Problems,” in Proc. 2011 IEEE International Symposium on EMC, Long Beach, CA, pp. 596-601, Aug. 2011.
  9. Tadatoshi Sekine and Hideki Asai, “Full-Wave PEEC Time Domain Solver Based on Leapfrog Scheme,” in Proc. IEEE EPEPS 2011, San Jose, CA, pp. 181-184, Oct. 2011.
  10. Tadatoshi Sekine and Hideki Asai, “Simulation of Multiconductor Transmission Lines Using Block-Latency Insertion Method and Model Order Reduction Technique,” in Proc. EMC Compo 2011, Dubrovnik, Croatia, pp. 203-206, Nov. 2011.
  11. Tadatoshi Sekine, Tomoki Ishimaru, and Hideki Asai, “Transient Simulation of Multilayered Power Distribution Network Based on Block-Type Alternating Direction Implicit Scheme,” in Proc. APEMC 2012, Singapore, May 2012. [Best Student Paper Award Finalist]
  12. Tadatoshi Sekine, Hideki Asai, and John S. Lee, “Unified Circuit Modeling Technique for the Simulation of Electrostatic Discharge (ESD) Injected by an ESD Generator,” in Proc. 2012 IEEE International Symposium on EMC, Pittsburgh, PA, pp. 340-345, Aug. 2012.
  13. Tadatoshi Sekine and Hideki Asai, “Nonlinear Block-Type Leapfrog Scheme for the Fast Simulation of Multiconductor Transmission Lines with Nonlinear Drivers and Terminations,” in Proc. IEEE EPEPS 2012, Tempe, AZ, pp. 284-287, Oct. 2012.
  14. Tadatoshi Sekine and Hideki Asai, “Unconditionally Stable Explicit Method for the Fast 3-D Simulation of On-Chip Power Distribution Network with Through Silicon Via,” in Proc. ASP-DAC 2013, Yokohama, Japan, pp. 7-12, Jan. 2013.
  15. Tadatoshi Sekine and Hideki Asai, “Explicit and Unconditionally Stable Method for the Fast 3-D Simulation of Staked Chip Power Distribution Networks Connected by Through Silicon Via Arrays,” in Proc. DATE 2013 Friday Workshop, Grenoble, France, Mar. 2013.
  16. Tadatoshi Sekine and Hideki Asai, “Unconditionally Stable Explicit Method for the Fast 3-D Simulation of On-Chip Power Distribution Network,” in Proc. IEEE ECTC 2013, Las Vegas, NV, pp. 1094-1099, May 2013.
  17. Tadatoshi Sekine and Hideki Asai, “A Framework for the Simulation of Electrostatic Discharge Immunity Using the Unified Circuit Modeling Technique,” in Proc. 2013 IEEE International Symposium on EMC, Denver, CO, pp. 1-6, Aug. 2013. [Best Symposium Paper Award Finalist]
  18. Tadatoshi Sekine and Hideki Asai, “Optimum Implementation of a Locally Implicit Leapfrog Scheme for Fast Simulation of Inhomogeneously-Meshed Plane Structures,” in Proc. IEEE EPEPS 2013, San Jose, CA, pp. 47-50, Oct. 2013.
  19. Tadatoshi Sekine and Hideki Asai, “Efficient Modeling and Analysis of Multilayered Power Distribution Network by Using Conformal Mesh and Block-Type Leapfrog Scheme,” in Proc. IEEE EDAPS 2013, Nara, Japan, pp. 221-224, Dec. 2013.
  20. Tadatoshi Sekine and Hideki Asai, “Locally Stabilized Explicit Method for Fast Transient Analysis of Inhomogeneously-Meshed Plane Structures,” in Proc. 2014 IEEE International Symposium on EMC, Raleigh, NC, pp. 888-893, Aug. 2014.
  21. Tadatoshi Sekine, Kenjiro T. Miura, and Hideki Asai, “Electrostatic Field Simulations of Curved Conductors by Using Method of Moments Based on Isogeometric Analysis,” in Proc. EMC Europe 2014, Gothenburg, Sweden, pp. 192-195, Sep. 2014.
  22. Tadatoshi Sekine, Kenjiro T. Miura, and Hideki Asai, “Method of Moments Based on Isogeometric Analysis for Electrostatic Field Simulations of Curved Multiconductor Transmission Lines,” in Proc. IEEE EPEPS 2014, Portland, OR, pp. 195-198, Oct. 2014.
  23. Tadatoshi Sekine and Hideki Asai, “Fast Transient Simulation of Multilayered Power Delivery Network by Using the Stabilized Explicit Method” in Proc. 2015 IEEE International Symposium on EMC&SI, Santa Clara, CA, pp. 253-258, Mar. 2015.
  24. Tadatoshi Sekine and Hideki Asai, “Conformal Equivalent Circuit Model and Leapfrog Alternating Direction Implicit Formulation for Fast Simulation of Power Delivery Network,” in Proc. 2015 IEEE International Symposium on EMC and EMC Europe, Dresden, Germany, pp. 588-593, Aug. 2015. [Best Symposium Paper Award Finalist]
  25. Tadatoshi Sekine and Hideki Asai, “A Stabilized Leapfrog Scheme for Circuit-Based Analysis of Power Delivery Network,” in Proc. IEEE EPEPS 2015, San Jose, CA, pp. 21-23, Oct. 2015.
  26. Tadatoshi Sekine and Hideki Asai, “Meshless Modeling for Electrical-Thermal Co-Simulation of IR-Drop Analysis” in Proc. 2016 IEEE International Symposium on EMC, Ottawa, ON, Canada, pp. 182-186, Jul. 2016.
  27. Tadatoshi Sekine and Hideki Asai, “Enlarged Cell Technique for Conformal Equivalent Circuit Model of Power Delivery Network,” in Proc. IEEE EPEPS 2016, San Diego, CA, pp. 119-121, Oct. 2016.
  28. Tadatoshi Sekine, “Electromagnetic Simulation of Curved Objects Based on Isogeometric Analysis,” in Proc. 2017 IEEE Symposium on EMC+SIPI, Washington D.C., pp. 94-97, Aug. 2017.
  29. Tadatoshi Sekine, “An Estimation Method for the Capacitance Matrix of Bundle of Wires Based on Machine Learning,” in Proc. EMC Europe 2018, Amsterdam, The Netherlands, pp. 1004-1007, Aug. 2018.

国際会議(共著)

  1. Tomoki Ishimaru, Tadatoshi Sekine, and Hideki Asai, “Equivalent Properties Between Latency Insertion Method (LIM) and Semi-Implicit Numerical Integration Method,” in Proc. ITC-CSCC 2009, Jeju, Korea, Jul., 2009.
  2. Yuta Inoue, Tadatoshi Sekine, Takahiro Hasegawa, and Hideki Asai, “Fast Circuit Simulation Based on Parallel-Distributed LIM Using Cloud Computing System,” in Proc. ITC-CSCC 2009, Jeju, Korea, pp. 845-846, Jul., 2009.
  3. Yuta Inoue, Tadatoshi Sekine, and Hideki Asai, “GPGPU-Based Latency Insertion Method: Application to PDN Simulations,” in Proc. IEEE EDAPS 2009, Hong Kong, pp. 1-4, Dec., 2009.
  4. Yuta Inoue, Tadatoshi Sekine, and Hideki Asai, “Parallel-Distributed Block-LIM-Based Fast Circuit Simulation of Tightly Coupled Transmission Lines,” in Proc. IEEE ECTC 2010, Las Vegas, NV, pp. 657-662, Jun., 2010.
  5. Hiroki Kurobe, Tadatoshi Sekine, and Hideki Asai, “High-speed Transient Simulation of Power Distribution Network Based on ADE-LIM,” in Proc. ITC-CSCC 2010, Pattaya, Thailand, Jul., 2010.
  6. Hiroki Kurobe, Tadatoshi Sekine, and Hideki Asai, “Application of ADE-LIM to Multiconductor Transmission Lines with Nonlinear Drivers and Terminations,” in Proc. IEEE EDAPS 2010, Singapore, pp. 1-4, Dec., 2010.
  7. Yuta Inoue, Tadatoshi Sekine, and Hideki Asai, “GPGPU-Based ADE-FDTD Method for Fast Electromagnetic Field Simulation and Its Estimation,” in Proc. APMC 2011, Melbourne, Australia, pp. 733-736, Dec., 2011.
  8. Yusuke Hizawa, Hiroki Kurobe, Tadatoshi Sekine, and Hideki Asai, “Nonlinear Block Latency Insertion Method for Fast Simulation of Strongly Coupled Network with CMOS Inverters,” in Proc. IEEE EDAPS 2011, Hangzhou, China, pp. 1-4, Dec., 2011.
  9. Hiroki Kurobe, Tadatoshi Sekine, and Hideki Asai, “Predictor-Corrector Latency Insertion Method for Fast Transient Analysis of Ill-Constructed Circuits,” in Proc. ASP-DAC 2012, Sydney, Australia, pp. 365-370, Mar., 2012.
  10. Takahiro Takasaki, Tadatoshi Sekine, and Hideki Asai, “Fast Transient Analysis of Multiconductor Transmission Lines Using Nodal Block Relaxation (NBR) Method,” in Proc. ITC-CSCC 2012, Sapporo, Japan, Jul., 2012.
  11. Tsuyoshi Takada, Tadatoshi Sekine, and Hideki Asai, “Circuit/Electromagnetic Hybrid Simulation of Electrostatic Discharge in Contact Discharge Mode,” in Proc. EMC Europe 2012, Rome, Italy, pp. 1-6, Sep., 2012.
  12. Shingo Okada, Hiroki Kurobe, Tadatoshi Sekine, and Hideki Asai, “Fast Transient Analysis of Power Distribution Network Modeled by Unstructured Meshes by Using Locally Implicit Latency Insertion Method,” in Proc. IEEE EDAPS 2012, Taipei, Taiwan, pp. 21-24, Dec., 2012.
  13. Norio Nishizaki, Tadatoshi Sekine, and Hideki Asai, “An Explicit and Unconditionally Stable Finite Difference Scheme for the Fast Transient Analysis of a Power Distribution Network,” in Proc. IEEE EDAPS 2012, Taipei, Taiwan, pp. 25-28, Dec., 2012.
  14. Daisuke Honda, Tadatoshi Sekine, and Hideki Asai, “Macromodeling and Circuit Simulation of High-Speed Interconnects Based on Vector Fitting and Equivalent Circuit Synthesis,” in Proc. NCSP’13, Hawaii, HI, pp. 484-487, Mar., 2013.
  15. Tsuyoshi Takada, Tadatoshi Sekine, and Hideki Asai, “Effcient Circuit/Electromagnetic Hybrid Simulation for the Electrostatic Discharge Events,” in Proc. APEMC 2013, Melbourne, Australia, pp. 1-6, May, 2013.
  16. Shingo Okada, Tadatoshi Sekine, and Hideki Asai, “Locally Implicit Block-LIM for the Simulation of Multilayered PDN Modeled by Triangular Meshes,” in Proc. URSI AP-RASC 2013, Taipei, Taiwan, pp. 1-6, Sep., 2013.
  17. Daisei Nagata, Tadatoshi Sekine, and Hideki Asai, “Fast Transient Analysis of 3-D Stacked On-Chip Power Distribution Network with Power/Ground Through Silicon Vias by Using Block Latency Insertion Method,” in Proc. IEEE EDAPS 2013, Nara, Japan, pp. 64-67, Dec., 2013.
  18. Takahiro Takasaki, Tadatoshi Sekine, and Hideki Asai, “Efficient PDN simulation by Locally Implicit Latency Insertion Method Based on Rectangular Meshes,” in Proc. IEEE EDAPS 2013, Nara, Japan, pp. 76-79, Dec., 2013.
  19. Takaaki Hojo, Tadatoshi Sekine, and Hideki Asai, “Fast Transient Analysis of Power/Ground Planes Based on Multi-Rate Locally Implicit Latency Insertion Method,” in Proc. IEEE EDAPS 2013, Nara, Japan, pp. 80-83, Dec., 2013.
  20. Shingo Okada, Tadatoshi Sekine, and Hideki Asai, “Nonlinear Locally Implicit LIM for the Simulation of PDN Modeled by Triangular Meshes,” in Proc. IEEE EDAPS 2013, Nara, Japan, pp. 84-87, Dec., 2013.
  21. Tsuyoshi Takada, Tadatoshi Sekine, and Hideki Asai, “Hybrid Simulation of ESD Events by SPICE-Like and Finite-Difference Time-Domain Methods,” in Proc. IEEE EDAPS 2013, Nara, Japan, pp. 197-200, Dec., 2013.
  22. Takahiro Takasaki, Tadatoshi Sekine, and Hideki Asai, “HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines,” in Proc. ASP-DAC 2014, Singapore, pp. 774-779, Jan., 2014.
  23. Mikito Hirata, Tadatoshi Sekine, and Hideki Asai, “Locally Implicit Finite-Volume Time-Domain Method for the Simulation of Small Conductive Objects,” in Proc. ITC-CSCC 2014, Phuket, Thailand, Jul., 2014.
  24. Kazuki Sakamoto, Tadatoshi Sekine, and Hideki Asai, “Comparison Between Latency Insertion Method (LIM) and Relaxation Method in Thermal Integrity Analysis,” in Proc. APEMC 2015, Taipei, Taiwan, pp. 341-344, May, 2015.
  25. Kaoru Nakagaki, Tadatoshi Sekine, and Hideki Asai, “Fast Transient Simulation of Power Distribution Network Based on Stabilized Explicit Method,” in Proc. APEMC 2015, Taipei, Taiwan, pp. 345-348, May, 2015.
  26. Ikki Arakaki, Tadatoshi Sekine, and Hideki Asai, “Triangular Subcell Method for Efficient Equivalent Circuit Modeling of Power Delivery Network,” in Proc. ITC-CSCC 2015, Seoul, Korea, Jul., 2015.
  27. Ngo Ha Anh, Tadatoshi Sekine, and Hideki Asai, “A Comparison Between Latency Insertion Method and Relaxation Method in Transient Thermal Analysis,” in Proc. APEMC 2016, Shenzhen, China, pp. 166-169, May, 2016.
  28. Ikki Arakaki, Tadatoshi Sekine, and Hideki Asai, “Fast Simulation of Multilayered Power Delivery Network using Multilayered Triangular Subcell Method and Block-Type Leapfrog Scheme,” in Proc. URSI AP-RASC 2016, Seoul, Korea, pp. 925-928, Aug., 2016.
  29. Ngo Ha Anh, Tadatoshi Sekine, and Hideki Asai, “Subgrid-Based Equivalent Circuit for Transient Thermal Analysis Using Latency Insertion Method,” in Proc. 2017 IEEE Symposium on EMC+SIPI, Washington D.C., pp. 760-765, Aug., 2017.
  30. Kenjiro T. Miura, Gobithaasan R.U., Shin Usuki, and Tadatoshi Sekine, “Discrete Tau-Curve,” in Proc. ACDDE 2019, Penang, Malaysia, Jul., 2019.
  31. Hayato Naojima and Tadatoshi Sekine, “Stabilized Explicit Isogeometric Analysis (SE-IGA) for Efficient Modeling and Analysis of 2-D Curved Structures,” in Proc. EMC Europe 2019, Barcelona, Spain, pp. 825-830, Sep. 2019.

国内研究会・大会

  1. 関根惟敏, 浅井秀樹, “節点方程式化に基づく電源グリッドの緩和法解析”, 信学技報, vol. 107, no. 184, NLP2007-36, pp. 1-6, 2007年8月
  2. 關根惟敏, 浅井秀樹, “LIMに基づく非線形回路の高速解析手法”, 電気学会研究会資料, pp. 29-34, 2009年11月
  3. 關根惟敏, 浅井秀樹, “反復LIMによる大規模線形回路網の高速過渡解析とその評価”, 第25回エレクトロニクス実装学会春季講演大会講演論文集, pp. 19-20, 2011年3月
  4. 關根惟敏, 浅井秀樹, “ブロックLIMと次数縮小モデルを用いた非線形素子を含む多導体系の高速シミュレーション”, 信学技報, vol. 111, no. 242, CAS2011-41, pp. 49-54, 2011年10月
  5. 關根惟敏, 浅井秀樹, “Leapfrog法と遅延PEEC法に基づく時間領域電磁界シミュレーション”, 信学技報, vol. 112, no. 73, EMCJ2012-21, pp. 71-76, 2012年6月
  6. 關根惟敏, 浅井秀樹, “等角メッシュモデルとブロック型Leapfrog 法を用いた多層電源分配回路網の高速シミュレーション”, 信学技報, vol. 113, no. 454, VLD2013-136,, pp. 13-18, 2014年3月
  7. 關根惟敏, “機械学習を用いた車載ワイヤーハーネスのキャパシタンス行列計算”, 信学技報, vol. 118, no. 104, MW2018-21, pp. 19-24, 2018年6月

国内研究会・大会(共著)

  1. 石丸友紀, 關根惟敏, 浅井秀樹, “セミ・インプリシット数値積分法に基づく電源分配回路網解析”, 信学技報, vol. 109, no. 199, CAS2009-29, pp. 31-35, 2009年9月
  2. 井上雄太, 關根惟敏, 浅井秀樹, “GPGPU-LIMに基づく回路シミュレーションとその評価”, 信学技報, vol. 109, no. 199, CAS2009-29, pp. 37-42, 2009年9月
  3. 井上雄太, 關根惟敏, 浅井秀樹, “並列分散型ブロックLIMによる強結合伝送線路の高速過渡解析”, 信学技報, vol. 109, no. 300, CAS2009-49, pp. 25-30, 2009年11月
  4. 黒部裕貴, 關根惟敏, 浅井秀樹, “ADE-LIMに基づく電源分配回路網の高速過渡解析”, 信学技報, vol. 110, no. 86, CAS2010-2, pp. 7-12, 2010年6月
  5. 黒部裕貴, 關根惟敏, 浅井秀樹, “ADE-LIMによる強結合伝送線路の高速過渡解析と評価”, 信学技報, vol. 110, no. 283, CAS2010-78, pp. 71-76, 2010年11月
  6. 石丸友紀, 關根惟敏, 浅井秀樹, “ADI法を適用したブロックLIMに基づく多層電源分配網解析”, 第25回エレクトロニクス実装学会春季講演大会講演論文集, pp. 19-20, 2011年3月
  7. 井上雄太, 關根惟敏, 浅井秀樹, “マルチレートブロックLIMによる強結合伝送線路の高速過渡解析”, 信学技報, vol. 110, no. 470, EMCJ2010-124, pp. 33-38, 2011年3月
  8. 樋澤佑修, 黒部裕貴, 關根惟敏, 浅井秀樹, “block-LIMに基づくCMOS素子を含む大規模回路網の高速解析手法”, 信学技報, vol. 111, no. 99, EMCJ2011-40, pp. 37-42, 2011年6月
  9. 黒部裕貴, 關根惟敏, 浅井秀樹, “予測子-修正子法を適用したLIMによる大規模回路網の高速過渡解析”, 信学技報, vol. 111, no. 242, CAS2011-39, pp. 37-42, 2011年10月
  10. 黒部裕貴, 關根惟敏, 浅井秀樹, “HIE-LIMによる任意形状を持つ電源分配網の高速過渡解析”, 第26回エレクトロニクス実装学会春季講演大会講演論文集, pp. 150-151, 2012年3月
  11. 髙田剛, 關根惟敏, 浅井秀樹, “静電放電現象のための回路/電磁界混合シミュレーション”, 信学技報, vol. 112, no. 73, EMCJ2012-20, pp. 65-70, 2012年5月
  12. 高崎貴大, 關根惟敏, 浅井秀樹, “節点ブロック緩和法を用いた多導体伝送線路の高速シミュレーション”, 信学技報, vol. 112, no. 113, CAS2012-15, pp. 81-85, 2012年7月
  13. 本多大介, 關根惟敏, 浅井秀樹, “伝送線路特性のベクトルフィッティングによる有理関数近似と等価回路合成”, 信学技報, vol. 112, no. 320, VLD2012-92, pp. 189-194, 2012年11月
  14. 岡田慎吾, 關根惟敏, 浅井秀樹, “電源分配回路網の非構造メッシュ化と局所陰的LIMによる高速過渡解析”, 信学技報, vol. 112, no. 320, VLD2012-96, pp. 213-218, 2012年11月
  15. 西崎統大, 關根惟敏, 浅井秀樹, “陽的かつ無条件安定な手法による電源分配回路網の高速過渡解析”, 信学技報, vol. 112, no. 320, VLD2012-97, pp. 219-224, 2012年11月
  16. 関口雄太, 關根惟敏, 浅井秀樹, “CIP法に基づく微細構造を含む電磁界解析に関する一考察”, 信学技報, vol. 112, no. 418, CAS2012-80, pp. 83-88, 2013年1月
  17. 中島悠貴, 關根惟敏, 浅井秀樹, “近似的陰解法に基づく有損失電源分配回路網の高速過渡解析”, 信学技報, vol. 112, no. 418, CAS2012-79, pp. 77-82, 2013年1月
  18. 岡田慎吾, 關根惟敏, 浅井秀樹, “局所陰的ブロックLIMによる非構造メッシュでモデル化された多層電源分配網の高速過渡解析”, DAシンポジウム2013論文集, pp. 109-114, 2013年8月
  19. 永田大成, 關根惟敏, 浅井秀樹, “電源/グランドTSVを含む三次元積層型電源分配回路網のブロックLIMによる効率的な過渡解析”, 信学技報, vol. 113, no. 224, CAS2013-36, pp. 1-6, 2013年9月
  20. 北條貴亮, 關根惟敏, 浅井秀樹, “電源分配回路網の高速過渡解析のためのマルチレート局所陰的LIM”, 信学技報, vol. 113, no. 224, CAS2013-37, pp. 7-12, 2013年9月
  21. 髙田剛, 關根惟敏, 浅井秀樹, “LIM/FDTD混合手法による静電気放電シミュレーション”, 信学技報, vol. 113, no. 423, EMCJ2013-113, pp. 13-18, 2014年1月
  22. 坂本和基, 關根惟敏, 浅井秀樹, “ブロックLIMを用いたシリコン貫通ビアを伴う三次元集積回路の高速解析”, 2015年電子情報通信学会総合大会 基礎・ 境界講演論文集, p. 21, 2015年3月
  23. 坂本和基, 關根惟敏, 浅井秀樹, “熱解析におけるLatency Insertion Method (LIM)と緩和法の比較”, 信学技報, vol. 114, no. 122, CAS2014-28, pp. 147-152, 2014年7月
  24. 中垣薫, 關根惟敏, 浅井秀樹, “安定化陽解法による不均一分布定数回路網の高速過渡解析”, 信学技報, vol. 114, no. 122, CAS2014-29, pp. 153-157, 2014年7月
  25. 平田幹人, 關根惟敏, 浅井秀樹, “局所陰的FVTD法による微細メッシュを含む電磁界解析の高速化”, 2015年電子情報通信学会総合大会 基礎・ 境界講演論文集, p. 247, 2015年3月
  26. 及川陽平, 關根惟敏, 浅井秀樹, “マクスウェルの方程式に基づく安定化陽的FETD法による高速電磁界過渡解析”, 信学技報, vol. 116, no. 467, CAS2016-133, pp. 105-109, 2017年2月
  27. 中村昌弘, 井上雄太, 關根惟敏, 浅井秀樹, “安定化陽的メッシュレス法による電磁界解析”, 信学技報, vol. 117, no. 503, CAS2017-155, pp. 123-128, 2018年3月
  28. Hayato Naojima, “Efficient Modeling and Analysis of Curved Structure Based on Stabilized Explicit Isogeometric Analysis”, Midland Student Express 2019 Spring, IEEE MTT-S Nagoya Chapter, Apr. 2019.
  29. 直島勇斗, 關根惟敏, “一次元電磁界解析におけるアイソジオメトリック解析への安定化陽解法の適用”, 信学技報, vol. 118, no. 144, EST2018-11, pp. 39-44, 2018年7月