Books
b15a On-chip High-Voltage Generator Design: Design Methodology for Charge Pumps, 2nd edition, Springer (2015). Link
b12a On-chip High-Voltage Generator Design, Springer (2012). Link
b02a Power Aware Design Methodologies (Editors: M. Pedram and J. M. Rabaey), Kluwer Academic Publishers (2002), Low Power Memory Design (Y. Oowaki and T. Tanzawa), pp. 52-73. Link, c.f. low power circuit design for flash memories
Journal papers
p23b T. Hashimoto, H. Nekozuka, Y. Toeda, M. Otani, Y. Fukuoka, and T. Tanzawa, A −31.7 dBm Sensitivity 0.011mm2 CMOS On-Chip Rectifier for Microwave Wireless Power Transfer, Electronics, 12/6, 1400 (2023)
p23a K. Nono and T. Tanzawa, One-Dimensional Maximum Power Point Tracking Design of Switched-Capacitor Charge Pumps for Thermoelectric Energy Harvesting, Electronics, 12/5, 1203 (2023)
p22e A. Ballo, A. D. Grasso, G. Palumbo, T. Tanzawa, A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers, IEEE Access, Nov. 2022.
p22d T. Hashimoto and T. Tanzawa, Design Space Exploration of Antenna Impedance and On-Chip Rectifier for Microwave Wireless Power Transfer, Electronics, 11/19, 3218 (2022)
p22c T. Nomura and T. Tanzawa, More Enhanced Swing Colpitts Oscillators: A Circuit Analysis, Electronics, 11/18, 2808 (2022)
p22b J. Kondo and T. Tanzawa, Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory, Electronics 11/13 1926 (2022)
p22a Y. Demura and T. Tanzawa, Design of Switched-Capacitor DC-DC Voltage-Down Converters Driven by Highly Resistive Energy Transducer, Electronics 11/12, 1874 (2022)
p21f Y. Tone and T. Tanzawa, “An Optimum Structure of Scalable Capacitors in 3D Crosspoint Memory Technology”, Electronics 2021, 10(22), 2755; https://doi.org/10.3390/electronics10222755.
p21e Y. Sugiura and T. Tanzawa, “Pre-Emphasis Pulse Design for Random-Access Memory,” Electronics 2021, 10(12), 1454; doi: 10.3390/electronics10121454
p21d K. Koketsu and T. Tanzawa, “Design of a Charge Pump Circuit and System with Input Impedance Modulation for a Flexible-Type Thermoelectric Generator with High-Output Impedance,” Electronics 2021, 10(10), 1212; doi: 10.3390/electronics10101212
p21c Y. Ishida, T. Tanzawa, “A Fully Integrated AC-DC Converter in 1 V CMOS for Electrostatic Vibration Energy Transducer with an Open Circuit Voltage of 10 V,” Electronics 2021, 10(10), 1185; DOI: 10.3390/electronics10101185
p21b A. Ballo, A. D. Grasso, G. Palumbo, T. Tanzawa, “Charge Pumps for Ultra-Low-Power Applications: Analysis, Design and New Solutions,” IEEE Transactions on Circuits and Systems II: Express Briefs ( Early Access ), Apr. 2021. DOI: 10.1109/TCSII.2021.3070889
p20a “Linear distribution of capacitance in Dickson charge pumps to reduce rise time, ” International Journal of Circuit Theory & Applications, Jan. 2020.
p18b On the Output Impedance and an Output Current – Power Efficiency Relationship of Dickson Charge Pump Circuits, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, No. 11, pp. 1664-7, 2018. (DOI: 10.1109/TCSII.2017.2764023).
p18a Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology, IEICE Transactions on Electronics, vol.E101-C, no.1, pp.78-81, Jan. 2018. (DOI: 10.1587/transele.E101.C.78)
p17a An Analytical Model of Charge Pump DC-DC Voltage Multiplier Using Diodes, T. Tanzawa, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, vol. E-100-A, No. 5, pp. 1137-1144, May 2017.
p16d Innovation of Switched-Capacitor Voltage Multiplier: Part 3: State of the Art of Switching Circuits and Applications of Charge Pumps, T. Tanzawa, IEEE Solid-State Circuits Magazine, vol. 8, No. 3, pp. 63-73, Aug. (2016).
p16c Innovation of Switched-Capacitor Voltage Multiplier: Part 2: Fundamentals of the charge pump, T. Tanzawa, IEEE Solid-State Circuits Magazine, vol. 8, No. 2, pp. 83-92, Jun. (2016).
p16b Innovation of Switched-Capacitor Voltage Multiplier: Part 1: A Brief History, T. Tanzawa, IEEE Solid-State Circuits Magazine, vol. 8, No. 1, pp. 51-59, Jan. (2016).
p16a An Analytical Model of AC-DC Charge Pump Voltage Multipliers, T. Tanzawa, IEICE Transactions on Electronics, Vol. E99-C, No.1, pp. 108-118, Jan. (2016)
p14a An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers with Area Power Balance, T. Tanzawa, IEEE Transactions on Power Electronics, pp. 534 – 538, Vol. 29, No. 2, (2014).
p12a A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation, T. Tanzawa, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 2351-2355, Vol. 20, No. 12, (2012).
p11b A Switch-Resistance-Aware Dickson Charge Pump Model for Optimizing Clock Frequency, T. Tanzawa, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, No. 6, pp. 336 – 340, (2011).
p11a A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm nand Flash Cells, A. Torsi, Z. Yijie, H. Liu, T. Tanzawa, A. Goda, P. Kalavade, K. Parat, IEEE Transactions on Electron Devices, Vol. 58, No. 1, pp. 11 – 16, (2011).
p10b On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area, T. Tanzawa, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, No. 10, pp. 2602 – 2608, (2010).
p10a A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs, T. Tanzawa, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 7, pp. 527 – 530, (2010).
p05a A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters, T. Tanzawa, K. Agawa. H. Shibayama. R. Terauchi. K. Hisano. H. Ishikuro. S. Kousai. H. Kobayashi, H. Majima, T. Takayama, M. Koizumi, F. Hatori, IEICE Transactions on Electronics, Vol. E88-C, No.4, pp.490-495, Apr. (2005).
p02c High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories, T. Tanzawa, Y. Takano, K. Watanabe, S. Atsumi, IEEE Journal of Solid-State Circuits, Vol. 37, No. 10, pp. 1318 – 1325, (2002).
p02b A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller, T. Tanzawa, A. Umezawa, T. Taura, H. Shiga, T. Hara, Y. Takano, T. Miyaba, N. Tokiwa, K. Watanabe, H. Watanabe, K. Masuda, K. Naruke, H. Kato, S. Atsumi, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1485 – 1492, (2002).
p02a Circuit techniques for a 1.8-V-only NAND flash memory, T. Tanzawa, T. Tanaka, K. Takeuchi, H. Nakamura, IEEE Journal of Solid-State Circuits, Vol. 37, No. 1, pp. 84 – 89, (2002).
p01a Wordline voltage generating system for low-power low-voltage flash memories, T. Tanzawa, A. Umezawa, M. Kuriyama, T. Taura, H. Banba, T. Miyaba, H. Shiga, Y. Takano, S. Atsumi, IEEE Journal of Solid-State Circuits, Vol. 36, No. 1, pp. 55 – 63, (2001).
p00b A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme, S. Atsumi, A. Umezawa, T. Tanzawa, T. Taura, H. Shiga, Y. Takano, T. Miyaba, M. Matsui, H. Watanabe, K. Isobe, S. Kitamura, S. Yamada, M. Saito, S. Mori, T. Watanabe, IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, pp. 1648 – 1654, (2000).
p00a Design of a sense circuit for low-voltage flash memories, T. Tanzawa, Y. Takano, T. Taura, S. Atsumi, IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, pp. 1415 – 1421, (2000).
p99b Optimization of word-line booster circuits for low-voltage flash memories, T. Tanzawa, S. Atsumi, IEEE Journal of Solid-State Circuits, Vol. 34, No. 8, pp. 1091 – 1098, (1999).
p99a A CMOS bandgap reference circuit with sub-1-V operation, H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui, IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 670 – 674, (1999).
p98a A multipage cell architecture for high-speed programming multilevel NAND flash memories, K. Takeuchi, T. Tanaka, T. Tanzawa, IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp. 1228 – 1238, (1998).
p97c A dynamic analysis of the Dickson charge pump circuit, T. Tanzawa, T. Tanaka, IEEE Journal of Solid-State Circuits, Vol. 32, No. 8, pp. 1231 – 1240, (1997).
p97b A stable programming pulse generator for single power supply flash memories, T. Tanzawa, T. Tanaka, IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, pp. 845 – 851, (1997).
p97a A compact on-chip ECC for low cost flash memories, T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, pp. 662 – 669, (1997).
p92b Quantum Mechanics of a Particle on a Curved Surface Comparison of Three Different Approaches, M. Ikegami, Y. Nagaoka, S. Takagi and T. Tanzawa, Prog. Theor. Phys., Vol. 88, No. 2, pp. 229-249, (1992).
p92a Quantum Mechanics of a Particle Confined to a Twisted Ring, S. Takagi and T. Tanzawa, Prog. Theor. Phys., Vol. 87, No. 3, pp. 561-568, (1992).
Conference papers
S. Tanabe, Evaluation of DC/DC converter for hybrid power supply of thermoelectric generator and battery, C-12-2, Sep. 2022 (In Japanese)
The Origin of the Output Resistance in subthreshold Operation CMOS Latch-type RF-DC Charge Pump Circuits, T. Kotsubo, C-12-3, Sep. 2022 (In Japanese)
Proposal of a Design Flow for Minimum Input-Power Rectenna Having Antenna and On-Chip Rectifier, T. Hashimoto, C-12-4, Sep. 2022 (In Japanese)
Dependence of Boosting time of Fast Boost Converters on Variation in Parasitic Resistance of Inductor and Switching MOSFETs, Y. Kanayama, C-12-5, Sep. 2022 (In Japanese)
T. Hashimoto, Antenna/On-Chip-Rectifier Co-Design Methodology for Micro-Watt Microwave Wireless Power Transfer, 65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022).
J. Kondo, Pre-emphasis pulse design for ABL sensing of NAND, IEICE general conference, C-12-8, Mar. 2022. (In Japanese)
Y. Kanayama, Ramp-up performance limit of boost converters, IEICE general conference, C-12-23, Mar. 2022. (In Japanese)
R. Kotsubo, Modeling of Latched RF-DC Converters, IEICE general conference, C-12-19, Mar. 2022. (In Japanese)
Y. Kotoya, Regulator design for resonator-oscillator-rectifier booster, IEICE general conference, C-12-22, Mar. 2022. (In Japanese)
S. Tanabe, Modeling of Buck converter for TEG-Battery hybrid system, IEICE general conference, C-12-20, Mar. 2022. (In Japanese)
Y. Demura, Design of switched-capacitor DC-DC converters driven by transducers with high output impedance, IEICE general conference, C-12-21, Mar. 2022. (In Japanese)
c21iK. Nono, T. Tanzawa, “A Design of Charge Pump System with Maximum Power Point Tracking for Low Cost Thermoelectric Energy Harvesting,” IEICE society conf., C-12-3, Sep. 2021. (In Japanese)
c21h T. Hashimoto, T. Tanzawa, “An Optimum Design of Antenna and On-chip Rectifier for Micro-watt Microwave Wireless Power Transfer,” IEICE society conf., C-2-19, Sep. 2021. (In Japanese)
c21g H. Makino, T. Tanzawa, “A Low Power Design for NAND Flash with 1.2V I/O Power Supply,” IEICE society conf., C-12-21, Sep. 2021. (In Japanese)
c21f Y. Sakamoto, T. Tanzawa, “A Design of DC-DC Converter for Thermoelectric Energy Harvesting with Battery Backup,” IEICE society conf., C-12-1, Sep. 2021. (In Japanese)
c21e Y. Ishida, T. Tanzawa, “Design of interface circuits fabricated in 1V CMOS for electrostatic energy transducer with an open circuit voltage over 10V,” IEICE Technical Committee Conference on Integrated Circuits and Devices, Aug. 2021. (In Japanese)
c20h Y. Sakamoto and T. Tanzawa, “An Experimental Study of Power Converter System with Battery and Thermoelectric Energy Transducer Connected in Series,” IEICE society conf., C-12-9, Sep. 2020.
c20g Y. Ishida and T. Tanzawa, “A process- and temperature- tolerant fully integrated shunt regulator,” IEICE society conf., C-12-8, Sep. 2020.
c20f Y. Tabuchi and T. Tanzawa, “Mapping of Optimum Circuit Topology for Micro-Watt Rectenna in Output Voltage-Current Plane,” IEICE society conf., C-2-11, Sep. 2020.
c20e K. Koketsu and T. Tanzawa, “A Control Circuit Design of Power Converter with Time-Division Input Impedance Modulation for Energy Transducer with High Output Impedance,” IEICE Technical Committee Conference on Integrated Circuits and Devices, Aug. 2020. (In Japanese)
c20d Y. Sakamoto and T. Tanzawa, “A Power Converter System for Energy Harvesting Toward Zero Net Battery Power,” IEICE general conference, Mar. 2020.
c20c Y. Sugiura and T. Tanzawa, “An Optimum Pre-Emphasis Pulse Design for Random Access Memory,” IEICE general conference, Mar. 2020.
c20b T. Nomura and T. Tanzawa, “A Double Resonant Enhanced Swing Colpitts Oscillator for Extremely Low-Voltage DC/DC Boost Conversion,” IEICE general conference, Mar. 2020.
c20a J. Ye and T. Tanzawa, “An Optimum Circuit Design of clocked AC-DC charge pumps,” IEICE general conference, , Mar. 2020.
c19g Y. Yamazaki, “A Design Window for Device Parameters of Rectifying Diodes in 2.4 GHz Micro-watt RF Energy Harvesting,” IEEE APMC, Dec. 2019.
c19f Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time, K. Matsuyama and T. Tanzawa, IEEE ISCAS, B1L-H-4, May 2019.
c19e Toward a minimum-operating-voltage design of DC-DC charge pump circuits for energy harvesting, S. Tokuda and T. Tanzawa, IEEE ISCAS, C5L-K-5, May 2019.
c19d A Design of AC-DC Converters Fully Integrated in Standard CMOS for Electrostatic Vibration Energy Harvesting, Y. Ishida and T. Tanzawa, IEICE general conference, C-12-3, Mar. 2019.
c19c An Optimum Design of Thermal Energy Transducers and Power Converters for Small Form-Factor Thermoelectric Energy Harvester, K. Koketsu and T. Tanzawa, IEICE general conference, C-12-4, Mar. 2019.
c19b An Optimum Design of Micro-watt RF Energy Harvesters with RF-DC and DC-DC Conversions, Y. Tabuchi and T. Tanzawa, IEICE general conference, C-2-11, Mar. 2019.
c19a A Sensitivity Analysis of Power Conversion Efficiency of Rectifying Diodes on Their Device Parameters for Microwatt RF Energy Harvesting, Y. Yamazaki and T. Tanzawa, IEICE general conference, C-2-12, Mar. 2019.
c18g (Invited) Interface Circuit Design for Energy Harvesting: State of the Art and Challenges, T. Tanzawa, IEICE society conference, CI-3-1, Sep. 2018.
c18f A system design of clocked AC-DC converter for vibration energy harvesting, H. Kawauchi and T. Tanzawa, IEICE society conference, C-12-9, Sep. 2018.
c18e Formulation of minimal delay time with pre-emphasis pulses for dense parallel RC lines, K. Matsuyama and T. Tanzawa, IEICE society conference, C-12-5, Sep. 2018.
c18d A clocked AC-DC voltage multiplier for increasing the power conversion efficiency in vibration energy harvesting, H. Kawauchi and T. Tanzawa, IEICE general conference, C-12-16, Mar. 2018.
c18c An analysis on lower bounds of supply voltages for enhanced-swing Colpitts oscillators, Y. Kawakami and T. Tanzawa, IEICE general conference, C-12-17, Mar. 2018.
c18b Toward a minimum-operating-voltage design of DC-DC charge pump circuits for energy harvesting, S. Tokuda and T. Tanzawa, IEICE general conference, C-12-18, Mar. 2018.
c18a A closed-form expression for pre-emphasis pulses with minimal RC delay time, K. Matsuyama and T. Tanzawa, IEICE general conference, C-12-35, Mar. 2018.
c17a On-Chip Switched-Capacitor DC-DC Converter in Memory Technology: State of the Art and Challenges, T. Tanzawa, IEEE ECCTD (European Conference on Circuit Theory and Design), Sep. 2017.
c16a Design Challenge in 3D NAND Technology: a 4.8X Area- and 1.3X Power-Efficient 20V Charge Pump Using Tier Capacitors, T. Tanzawa, T. Murakoshi, T. Kamijo, T. Tanaka, J. McNeil, K. Duesman, IEEE Asian Solid-State Circuits Conference, Nov. 2016.
c15b A Comprehensive Optimization Methodology for Designing Charge Pump Voltage Multipliers, T. Tanzawa, IEEE International Conference on Circuits and Systems, pp. 1358-1361, May 2015.
c15a An Analytical Model of Multi-Sine AC-DC Voltage Multiplier, T. Tanzawa, IEEE International Conference on Circuits and Systems, pp. 1354-1357, May 2015.
c14b An Analytical Model of AC-DC Voltage Multipliers, T. Tanzawa, IEEE International Conference on Electronics Circuits and Systems, pp. 323-326, Dec. 2014.
c14a Design of DC-DC Switched-Capacitor Voltage Multiplier driven by DC Energy Transducer, T. Tanzawa, IEEE International Conference on Electronics Circuits and Systems, pp. 327-330, Dec. 2014.
c10b A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories, T. Tanzawa, T. Tanaka, S. Tamada, J. Kishimoto, S. Yamada, K. Kawai, T. Ichikawa, P. Chiang, F. Roohparvar, ESSCIRC, pp. 106 – 109, 2010
c10a NBTI stress relaxation design for scaling high-voltage transistors in NAND Flash memories, T. Tanzawa, IEEE International Memory Workshop (IMW), pp. 1 – 2, 2010.
c09b Dickson charge pump circuit design with parasitic resistance in power lines, T. Tanzawa, ISCAS, pp. 1763 – 1766, 2009. c
09a A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS, R. Zeng, N. Chalagalla, D. Chu, D. Elmhurst, M. Goldman, C. Haid, A. Huq, T. Ichikawa, J. Jorgensen, O. Jungroth, N. Kajla, R. Kajley, K. Kawai, J. Kishimoto, A. Madraswala, T. Manabe, V. Mehta, M. Morooka, K. Nguyen, Y. Oikawa, B. Pathak, R. Rozman, T. Ryan, A. Sendrowski, W. Sheung, Szwarc, Y. Takashima, S. Tamada, T. Tanzawa, T. Tanaka, M. Taub, D. Udeshi, S. Yamada, H. Yokoyama, IEEE International Solid-State Circuits Conference, pp. 236 – 237, 2009
c08a A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage, T. Tanzawa, ISCAS, pp. 2302 – 2305, 2008
c05a A low-IF CMOS single-chip Bluetooth EDR transmitter with digital I/Q mismatch trimming circuit, D. Miyashita, H. Ishikuro, T. Shimada, T. Tanzawa, S. Kousai, H. Kobayashi, H. Majima, K. Agawa, M. Hamada, F. Hatori, Digest of Technical Papers, Symposium on VLSI Circuits, pp. 298 – 301, 2005
c04a A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter, T. Tanzawa, H. Shibayama, R. Terauchi, K. Hisano, H. Ishikuro, S. Kousai, H. Kobayashi, H. Majima, T. Takayama, K. Agawa, M. Koizumi, F. Hatori, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 273 – 276, 2004
c02a A 44mm2 4-bank 8-word page read 64Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller, T. Tanzawa, A. Umezawa, T. Taura, H. Shiga, T. Hara, Y. Takano, T. Miyaba, N. Tokiwa, K. Watanabe, H. Watanabe, K. Masuda, K. Naruke, H. Kato, S. Atsumi, ISSCC, pp. 78 – 409, 2002
c00a A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme, S. Ataumi, A. Umezawa, T. Tanzawa, T. Taura, H. Shiga, Y. Takano, T. Miyaba, M. Matsui, H. Watanabe, K. Isobe, S. Kitamura, S. Yamada, M. Saito, S. Mori, T. Watanabe, Digest of Technical Papers. IEEE International Solid-State Circuits Conference, pp. 276 – 277, 2000.
c99a A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories, H. Shiga, T. Tanzawa, A. Umezawa, T. Taura, T. Miyaba, M. Saito, S. Kitamura, S. Mori, S. Atsumi, Digest of Technical Papers. Symposium on VLSI Circuits, pp. 33 – 36, 1999.
c98b Novel 0.44 μm2 Ti-salicide STI cell technology for high-density NOR flash memories and high performance embedded application, H. Watanabe, S. Yamada, M. Tanimoto, M. Matsui, S. Kitamura, K. Amemiya, T. Tanzawa, E. Sakagami, M. Kurata, K. Isobe, M. Takebuchi, M. Kanda, S. Mori, T. Watanabe, Technical Digest, International Electron Devices Meeting, pp. 975 – 978, 1998.
c98a A CMOS band-gap reference circuit with sub 1 V operation, H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui, Digest of Technical Papers, Symposium on VLSI Circuits, pp. 228 – 229, 1998.
c97d A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance, S. Satoh, H. Hagiwara, T. Tanzawa, K. Takeuchi, R. Shirota, IEEE IEDM, pp. 291-294, Dec. 1997.
c97a Circuit Technologies For A Single-1.8V Flash Memory, T. Tanzawa, T. Tanaka, K. Takeuchi, H. Nakamura, Digest of Technical Papers, Symposium on VLSI Circuits, pp. 63 – 64, 1997.
c97b A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories, K. Takeuchi, T. Tanaka, T. Tanzawa, Digest of Technical Papers, Symposium on VLSI Circuits, pp. 67 – 68, 1997.
c97a A 3.4-Mbyte/sec Programming 3-level NAND Flash Memory Saving 40% Die Size Per Bit, T. Tanaka, T. Tanzawa, K. Takeuchi, Digest of Technical Papers, Symposium on VLSI Circuits, pp. 65 – 66, 1997.
c96a A compact on-chip ECC for low cost flash memories, T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, Symposium on VLSI Circuits, pp. 74 – 75, 1996.
c95a A stable programming pulse generator for high-speed programming single power supply voltage flash memories, T. Tanzawa, T. Tanaka, Symposium on VLSI Circuits, pp. 73 – 74, 1995.
c94a A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories, T. Tanzawa, Y. Tanaka, T. Tanaka, N. Nakamura, H. Oodaira, K. Sakui, M. Momodomi, S. Shiratake, H. Nakano, Y. Oowaki, S. Watanabe, K. Ohuchi, F. Masuoka, Symposium on VLSI Circuits, pp. 65 – 66, 1994.
Lecture
l17a [Memorial lecture] “What I have learned through research and development on integrated charge pump circuits”, T. Tanzawa, IEICE technical report, CAS2016-96, ICTSSL2016-50, Jan. 2017
l14a “On-chip High-Voltage Charge Pump Design”, ESSCIRC Tutorial, Sep., 2014.
l12a 1st, 2nd, 3rd “On-chip High-voltage Generator Design”, ISCAS Tutorial, May 2012.
Patents
[1]. レクテナ装置及びレクテナ装置を設計する方法 [出願番号] 特願2019-169281 (2019年9月18日)
[2]. インピーダンス調整回路、電力変換素子及び電源素子 [出願番号] PCT/JP2019/016863 (2019年4月19日)
[3]. 電力変換装置及び電源装置 [出願番号] PCT/JP2018/045295 (2018年12月10日)
[4]. 駆動回路及び電子デバイス [出願番号] 特願2018-217136 (2018年11月20日)
[5]. 半導体装置及びその製造方法 [出願番号] PCT/JP2018/031369 (2018年8月24日)
[備考] 公開番号：WO2019/044705, 公開日：2019年3月7日
[6]. 電力変換回路及び電源装置 [出願番号] 特願2018-109038 (2018年5月21日)
[7]. インピーダンス調整回路、電力変換素子及び電源素子 [出願番号] 特願2018-81478 (2018年4月20日)
[8]. 電力変換装置及び電源装置 [出願番号] 特願2017-246692 (2017年12月22日)
[9]. 半導体装置及びその製造方法 [出願番号] 特願2017-168814 (2017年9月1日)
Total: 250 US granted patents Link and 61 Japan granted patents in total as of Sep. 2019.